Unofficial pages of the course Computer Architecture 2
About the course:
This course studies architectural components
of computer systems:
processor, memory, buses, and IO devices.
The course considers design approaches
which allow us to achieve the desired
computer system properties:
performance, price, power consumption, reliability.
The course assumes basic knowledge in
programming (C, assembly) and digital design
(logic gates, flip-flops, 3-state drivers).
The main fields of interest are:
architectural features of general purpose computers,
organizational details of the processor and memory hierarchy,
exploiting the parallelism at the levels of
instructions, vector instructions and threads.
Unfortunately, the English version of the course
does not offer lectures.
However, you can study the course material
from the reference text by David Patterson and John Hennesy,
and come to discuss the problems with lecturers
(please arrange the meeting by e-mail).
The course includes two mandatory lab exercises (see below).
The exam shall include modified problem questions from the textbook.
D. A. Patterson, J. L. Hennessy,
Computer Organization & Design,
The Hardware/Software Interface,
Morgan Kaufmann Pub., Fourth edition, 2007.
mixing C with assembly
influence of arcitectural features to software performance
The course can be passed
either through partial exams (mid-term, final),
or through a full exam.
In both cases we require at least 50% points
of the total aggregate exam score, and
a sufficient score at the laboratory exercises.
Please contact the course assistant whenever
you are ready to show your lab solutions.
The exams consist of problems which will be
similar to laboratory exercises and
the exercises from the textbook.
Problems related to the textbook
will be designed as shown in the following
The course covers the following sections from the textbook:
Performance: sections 1.1-1.5
CPU performance, CPI, instruction classes (exercises 1.3-1.7)
MIPS instruction architecture: sections 2.1-2.12
binary instruction format (exercises 2.10-2.11)
shift instructions (exercise 2.14)
translating C to assembly (exercises 2.18-2.21)
sign extension, large constants, branch range, addressing modes (exercises 2.24-2.27)
Single-cycle organization: sections 4.1-4.3
control signals (exercises 4.1-4.4)
timing (exercises 4.6-4.7)
case-studies (exercise 4.11)
Mid-term exam (includes the first lab exercise)
Pipelined organization: sections 4.4-4.11, 4.13-4.14
pipeline timing (exercise 4.12)
pipeline hazards (exercise 4.13-4.14)
impact of the instruction architecture (exercise 4.15)
multiple-issue CPUs (exercises 4.28-4.29)
Caches: sections 5.1-5.3
cache design (exercises 5.2-5.4)
impact to CPU performance (exercise 5.7)
Virtual memory: sections 5.4-5.5
design end performance (exercises 5.10-5.12)
Multi-core computers: sections 7.1-7.6
hardware multi-threading (exercise 7.12)
Final exam (includes all coursework and lab exercises)
Cliff Click on Computer Architecture for large Java programs
Intel Technology Journal
David Patterson: The Trouble With Multicore
All comments are welcome: